1. Field of the Invention
The present invention relates to a method for controlling a precharge timing of a memory device and an apparatus thereof, and more particularly to a method for controlling a precharge timing of a memory device and an apparatus thereof that can make the precharge timing of a bit line performed after a normal operation of the memory device and the precharge timing of the bit line after a refresh operation different from each other.
2. Description of the Prior Art
Generally, a volatile memory device (hereinafter referred to as a “memory device”) has three operation modes: a mode for storing data in memory cells (i.e., write mode), a mode for reading out the data from the memory cells (i.e., read mode) and a mode for restoring the data (i.e., refresh mode) at predetermined intervals so as to prevent the stored data from vanishing.
In performing such operation modes, each memory cell is composed of a cell transistor and a cell capacitor. By turning on a word line connected to a gate of the cell transistor, the data stored in the cell capacitor is read out through a bit line (in the read mode) or the data written from an outside is stored in the cell capacitor through the bit line (in the write mode).
In order to perform the above-described read operation, write operation and refresh operation, the cell transistor should be turned on by enabling the word line. This operation is called an active operation and an active command is a signal used for the active operation.
If the active command is applied, the cell transistor is turned on and the memory cell and a bit-line sense amplifier are connected with each other through the bit line.
If the word line is shifted to a high-level state by the active command, a charge sharing occurs between the memory cell and the bit line and the existing data is restored in the memory cell by the operation of the bit-line sense amplifier. After the data is restored in the memory cell, a precharge command is applied. This precharge command shifts the word line to a low-level state and precharges the bit line.
Meanwhile, in order to restore the existing data, the word line should be kept at a high level for a predetermined time and this time for which the word line is kept at a high level is called “tRAS.” In other words, the word line should be kept at a high level at least for the time tRAS after the active command is applied in order to stably perform the restore operation.
FIG. 1 is a view explaining a conventional method of performing a precharge operation in a memory device.
Referring to FIG. 1, a bank 100 includes a control signal generator 10, an auto precharge controller 11 and a precharge pulse generator 12, and a bank 110 includes a control signal generator 13, an auto precharge pulse generator 14 and a precharge pulse generator 15.
In FIG. 1, the auto precharge controllers 11 and 14 function to enable an auto precharge operation just after a read or write operation, and a refresh controller 16 functions to enable the precharge operation just after a self-refresh or auto-refresh operation. Although only two banks are illustrated in FIG. 1, four banks may be provided in the same manner.
Hereinafter, the operation of the circuit block of FIG. 1 will be explained in more detail.
The control signal generators 10 and 13 receive an input signal satvb that is a pulse signal, and generate a pulse signal trasminb that is a pulse signal (See FIG. 2a). Here, the control signal trasminb is a signal that is enabled as a low-level signal when a predetermined time elapses after a signal for activating the word line is applied. The control signal keeps the word line in an active state for the predetermined time tRAS, and then secures the time until the word line is turned off.
The auto precharge controllers 11 and 14, if the cause of the enabling of the word line is a normal operation such as a read with an auto precharge, a write with an auto precharge, etc., generate a precharge command when the control signal trasminb is shifted to a high-level state after the time tRAS. Here, the “read with an auto precharge” is a command for automatically precharging the bit line after the read operation, and the “write with an auto precharge” is a command for automatically precharging the bit line after the write operation.
The refresh controller 16, if the cause of the enabling of the word line is the auto refresh or self refresh operation, generates a precharge command when the control signal trasminb is shifted to a high-level state after the time tRAS.
The precharge pulse generators 12 and 15 receive output signal of the auto precharge controllers 11 and 14 and the refresh controller 16, the precharge command, etc., and generate an internal pulse for performing the precharge.
FIG. 2a is a view illustrating an example of the control signal generator of FIG. 1.
As illustrated in FIG. 2a, the control signal generator includes an inverter 21 for receiving a signal satvb, a delay unit 20 for receiving an output signal of the inverter 21, a NAND gate 22 for receiving an output signal of the delay unit 20 and the output signal of the inverter 21, and inverters 23 and 24 for driving an output signal of the NAND gate 22. The output signal of the inverter 24 is “trasminb.”
In FIG. 2a, the term “satvb” denotes a signal that is shifted from a high-level state to a low-level state if a signal for indicating an active operation is applied, and then shifted to a high-level state if a signal for indicating a precharge operation is applied (See FIGS. 10a to 10c).
FIG. 2b is a view illustrating an example of the delay unit 20 of the control signal generator illustrated in FIG. 2a. It can be recognized that the delay unit illustrated in FIG. 2b is not a general delay unit having an inverter chain.
The reason why the delay unit as illustrated in FIG. 2b is used is that a node A is shifted to a high-level state if the input signal satvb of the control signal generator is shifted to a low-level state. If the node A is shifted to a high-level state, a time period as much as tRAS, which is relatively greater than that obtained by the inverter chain, can be provided. Additionally, if the signal satvb is shifted to a high-level state by the precharge command, the node A is shifted to a low-level state. If the node A is shifted to a low-level state, a node B is shifted to a low-level state in a short time. Accordingly, the output signal trasminb can be shifted to a high-level state in a short time.
FIG. 3 is a view illustrating an example of an auto precharge controller illustrated in FIG. 1. This auto precharge controller generates the signal trasminb generated from the control signal generator and the precharge command apcg for the auto precharge operation.
The circuit of FIG. 3 includes an inverter 301 for receiving a signal pwrup, latch units 302 and 303, AND means 304 and 305, delay units 306 to 308 and AND means 309 and 310. As illustrated in FIG. 3, the AND means 304 and 305 receive an output signal of the inverter 301 and output signals of the latch units 302 and 303. The delay units 306 to 308 receive output signals of the AND means 304 and 305. The AND means 309 and 310 receive output signals of the delay units 306 to 308 and the output signals of the AND means 304 and 305, and output the signal apcg.
In FIG. 3, the term “with_apcgpb” denotes a signal for generating a low-level pulse when the command that requires the auto precharge operation such as the read with an auto precharge or the write with an auto precharge is applied from the outside (See FIGS. 10a to 10c). The term “pwrup” denotes a signal for setting an initial value of the memory device when the power is applied to the memory device. The signal pwrup is initially at a low level, but is fixed to a high level after a predetermined time elapses.
The operation of the circuit of FIG. 3 will now be explained.
Initially, the signal pwrup is at a low level, and thus a node N2 becomes high. If the read with an auto precharge or write with an auto precharge command is not applied, the signal with_apcgpb is at a high level, and thus a node N1 is kept at a low level. Additionally, if the word line is not activated, the signal trasminb is at a low level and the node N1 is also at a low level, a node N3 becomes low. Consequently, the node N4 is at a high level and the signal apcg is at a low level. If the power supply voltage goes over a predetermined level as the predetermined time elapses, the signal pwrup is shifted to a high-level state.
The circuit of FIG. 3 operates in a different manner according to the timing of the generation of the signal with_apcgpb, which will now be explained in detail.
First, if the read with an auto precharge or write with auto precharge command is applied before the time tRAS elapses after the active command is applied (See FIG. 10a), the circuit operates as follows.
When the active command is applied, the signal trasminb is at a high level (As described above, the signal trasminb become low after a predetermined time elapses after the active command). In this case, the node N3 becomes low and the node N4 becomes high irrespective of the state of the node N1. Accordingly, the signal apcg is kept at a low level and thus the precharge is not performed. That is, even if the precharge signal is applied by the read with an auto precharge or write with an auto precharge command (that is, even if the signal with_apcgpb causes a low-level pulse to be produced), the signal apcg is not enabled until the signal trasminb become low.
If the signal trasminb is shifted to a low-level state as the time goes by, the node N3 is shifted to a high-level state. At this time, since the node N4 is still at a high level, a signal having a pulse width corresponding to the delay time through the delay units 306, 307 and 308 is outputted. Accordingly, the precharge operation is performed. That is, if the timing when the signal with_apcgpb is applied is earlier than the timing when the signal trasminb is shifted to a low-level state, the precharge signal is not outputted irrespective of the applying of the signal with_apcgpb. In this case, the precharge operation is performed after the data is restored in the memory cells by the signal trasminb.
Second, if the read with an auto precharge or write with auto precharge command is applied after the time tRAS elapses after the active command is applied (See FIG. 10a), the circuit operates as follows.
As described above, when the active command is applied, the signal trasminb is shifted to a high-level state. Then, the node N3 becomes low and the node N4 becomes high irrespective of the state of the node N1. Accordingly, the signal apcg is kept at a low level and thus the precharge is not performed. Meanwhile, if the signal trasminb is first shifted to a low-level state in a state in which the read with an auto precharge or write with an auto precharge command is not applied (that is, in a state in which the signal with_apcgpb does not cause a low-level pulse to be produced), the node N1 is at a low level at that time, and thus there is no change in logic level of the nodes N3 and N4. Accordingly, the signal apcg is kept at a low level. Thereafter, if the low-level pulse with_apcgpb is generated when a predetermined time elapses after the signal trasminb is shifted to the low-level state, the node N1 is shifted to a high-level state. Accordingly, the node N3 is shifted to a high-level state and outputs the high-level pulse apcg to perform the precharge operation. That is, if the read with an auto precharge or write with an auto precharge command can supplement the time tRAS, the precharge operation is not performed just after the time tRAS, but is performed when an internal signal that makes the auto precharge possible is applied.
FIG. 4 is a view illustrating an example of the refresh controller illustrated in FIG. 1.
In FIG. 4, the term “arefp” denotes a signal that becomes a high-level pulse when it is required to restore the data in the memory cell after a predetermined time elapses in a normal operation. The term “sref” denotes a signal that indicates the entry into a self refresh mode, and become a high-level signal in the self refresh mode. The term “trasminbi” denotes a signal used in the i-th bank, and the term “trasminbj” denotes a signal used in the j-th bank. In the refresh mode such as a self refresh or auto refresh mode, all banks are simultaneously refreshed, and thus it can be recognized that if the signals trasminbi and trasminbj are simultaneously enabled, the present mode is the refresh mode.
The operation of the circuit of FIG. 4 will now be explained.
If the power is initially applied, the signal pwrup is kept at a low level, and thus the initial value of the node N1 becomes high. For reference, in a normal operation mode that is not the refresh mode, the signals arefp and sref are all at a low level, and thus the node N2 is at a low level.
The circuit of FIG. 4 operates in an auto refresh mode (i.e., the signal arefp is at a high level) and in a self refresh mode (i.e., the signal serf is at a high level).
In the auto refresh mode, the signal arefp becomes high. Accordingly, the node N1 becomes low and the node N2 also becomes low. Before the refresh operation is actually performed, the signals trasmini and trasminj are at a low level, and thus the node N3 becomes high. Accordingly, the node N4 becomes high, and an output signal sadly becomes low. As illustrated in FIG. 4, the low-level output signal sadly is fed back and turns off a PMOS transistor. Then, if the refresh operation is performed, the signals trasmini and trasminj become high. Accordingly, the node N3 becomes low and the node N4 also becomes low. The output signal sadly is kept at a low level irrespective of the logic level of the node N4. If the time tRAS elapses after all the banks are refreshed, all the signals trasmini and trasminj become low. Accordingly, the output signal sadly becomes a high pulse having a width corresponding to the delay time between the node N4 and the node N5. The high-level pulse output signal sadly turns on the PMOS transistor. Accordingly, the node N1 is shifted to a high-level state. The above-described process is repeated whenever the auto refresh operation is performed due to the high-level signal arefp.
Meanwhile, in the self refresh mode, the signal serf becomes high. In the self refresh mode, the node N2 is always at a low level irrespective of the logic level of the signal arefp. Accordingly, the output signal sadly becomes a high-level pulse whenever the signals trasmini and trasminj go from a high level to a low level.
Up to now, the construction and operation of the control signal generator, auto precharge controller and refresh controller as illustrated in FIG. 1 have been described.
FIG. 5 is a view illustrating an example of the precharge pulse generator illustrated in FIG. 1.
Referring to FIG. 5, a signal pcgp is a pulse signal that is applied as a high-level pulse when a compulsory precharge input is applied from the outside. A signal bk_add is a signal that indicates a bank address, and becomes high when the bank subject to precharge is designated. A signal add10 is the 10th address signal input from the outside. A signal rpcg is a signal for actually effecting the precharge operation by combining all cases for the precharge operation.
The operation of the circuit of FIG. 5 will be explained.
If the precharge command is applied from the outside, the signal pcgp becomes a high-level pulse. Additionally, if the address of the bank subject to precharge is applied, the signal bk_add becomes high, and if the address add10 is at a low level, the precharge operation is performed only for the corresponding bank. That is, the output of the NAND gate is at a low level by the signal pcgp in a normal operation state, and becomes high by the precharge command. Accordingly, the output signal rpcg becomes high to perform the precharge operation.
If the signal add10 is at a high level, even a bank that is not selected from the outside is precharged. In this case, all the banks are precharged.
If the precharge command is not applied from the outside, the output of the NAND gate becomes low. In this case, if the read with an auto precharge or write with an auto precharge is applied, the signal apcg becomes high. Accordingly, the output signal rpcg becomes a high-level pulse. Additionally, in the case of the precharge by the refresh, the signal sadly is at a high level, and thus the output signal rpcg becomes a high-level pulse. Accordingly, the output signal rpcg becomes a high-level pulse to perform the refresh operation.
According to the conventional circuits as described above, it can be recognized that the signal trasminb is applied in the same manner with respect to the auto precharge and the precharge by the refresh.
Although only one bank is precharged in the case of the auto precharge, however, all the banks are simultaneously precharged in the case of the precharge by the refresh. Due to this, the power becomes insufficient in the case of the precharge by the refresh, and thus a still longer time is required in restoring the data in the memory cells in the precharge operation by the refresh.